The present invention relates to forming features on a substrate, and more specifically, to methods for forming conductive features on a substrate.
Semiconductors and other devices are often formed on substrates such as silicon substrates. The devices are often connected using conductive features such as metallic contacts and conductive lines formed in or embedded in layers of materials formed on the substrate.
In this regard, a substrate may include a silicon or buried oxide layer and may include a variety of insulator oxide or nitride layers formed on the silicon or buried oxide layer. Cavities may be formed in the insulator layers that define the conductive features. The conductive features may be formed by depositing a conductive material in the cavities and over the exposed portions of the top layer of the substrate. A planarizing process such as chemical mechanical polishing (CMP) removes the conductive material from the top layer of the substrate, exposing the top layer of the substrate, and defining the conductive features.